日本語
English
Publications / Research Outputs
研究業績
論文誌、会議発表、学位論文を種別ごとに整理しています。
1
国際論文誌
エッジ AI、農業画像認識、CGLA アクセラレーションに関する査読付き論文です。
01.
"Lightweight YOLOX-based Green Onion Branching Point Detection for Automated Peeling on Edge Device"
Impact Factor: 0.72 (2026)
Links
PDF
[en]
Agricultural automation has become critical as labor continues to decline worldwide. In green onion processing, current peeling machines require significant manual work due to imprecise leaf removal. Prior edge detection methods were tested only on uniform stems of a single variety, limiting their practical use where green onions vary in morphology. The key challenge is developing a detection system that maintains performance across varieties and growth stages without frequent adjustments. Here we show that an improved YOLOX-nano model effectively detects branching points across diverse varieties, achieving a 0.929 detection score for the second branching point and 46 ms processing time on Jetson Orin Nano. Unlike edge detection methods, our deep learning approach handles variations in onion varieties and growth stages robustly and maintains performance under varying conditions. These results show that lightweight deep learning systems can reliably automate green onion peeling while achieving real-time performance on edge devices. The proposed system advances automated green onion peeling and could extend to similar agricultural tasks.
@article{ando2026lightweight,
author = {Takuto Ando and Iori Yamaguchi and Jun Shono and Takahiro Kawabe and Koji Uchida and Kosuke Shigematsu and Yusuke Inoue},
title = {Lightweight YOLOX-based Green Onion Branching Point Detection for Automated Peeling on Edge Device},
journal = {ICIC Express Letters},
volume = {20},
number = {8},
pages = {811--819},
year = {2026}
}
02.
"Design and Evaluation of Energy-Efficient Whisper Dot-Product Kernel Offloading on a CGLA Architecture"
2026
Impact Factor: 2.2 (2025)
[en]
In this paper, we implement and evaluate Whisper dot‐product kernel offloading on IMAX, a programmable coarse‐grained linear arrays (CGLAs) architecture. Whisper‐tiny.en profiling on an ARM Cortex‐A72 shows that dot‐product operations account for 90.6% of FP16 execution time and 87.1% of Q8_0 execution time. To address this kernel bottleneck, we combine kernel mapping, local‐memory sizing, and burst scheduling. The implementation uses inline FP16‐to‐FP32 conversion, 2‐way SIMD FMA on a 64‐bit datapath, column‐wise multithreading, and mixed execution in which aligned vector segments run on IMAX and residual segments run concurrently on the host CPU. We evaluate the design with an FPGA prototype and a 28 nm ASIC projection at 840 MHz. For Whisper‐tiny.en, 32 KB local memory and burst length 16 jointly minimize PDP and EDP. Under a TDP‐based cross‐platform comparison, the projected IMAX records a PDP of 11.58 J for Whisper‐tiny.en Q8_0, 2.35 lower than Jetson AGX Orin (27.16 J) and 10.48 lower than RTX 4090 (121.38 J). The same design extends to Whisper‐base.en and Whisper‐small.en, where the PDP gap narrows as 32 KB local‐memory coverage drops from 93.8% for tiny to about 66.5% for base and small. These results position IMAX as a programmable architecture for lower‐PDP local ASR in the tiny‐model regime.
@article{ando2026whisper,
author = {Takuto Ando and Yu Eto and Ayumu Takeuchi and Yasuhiko Nakashima},
title = {Design and Evaluation of Energy-Efficient Whisper Dot-Product Kernel Offloading on a CGLA Architecture},
journal = {Concurrency and Computation: Practice and Experience},
volume = {38},
pages = {e70826},
year = {2026},
doi = {10.1002/cpe.70826}
}
Design and Evaluation of Energy-Efficient Whisper Dot-Product Kernel Offloading on a CGLA Architecture
03.
"Efficient Kernel Mapping and Comprehensive System Evaluation of LLM Acceleration on a CGLA"
Impact Factor: 4.2 (2025)
[en]
Large Language Models (LLMs) demand substantial computational resources, resulting in high energy consumption on GPUs. To address this challenge, we focus on Coarse-Grained Reconfigurable Arrays (CGRAs) as an effective alternative that provides a trade-off between energy efficiency and programmability. This paper presents the first comprehensive, end-to-end evaluation of a non-AI-specialized CPU-Grounded Linear Array (CGLA) accelerator for the state-of-the-art Qwen3 LLM family. The architecture has a general-purpose, task-agnostic design, yet its flexible instruction set allows for domain-specific adaptations. This flexibility enables the architecture to achieve high efficiency for sustainable LLM inference. We assess the performance of our architecture on an FPGA prototype using the widely adopted llama.cpp framework. We then project its potential as a 28 nm ASIC and compare it against a high-performance GPU (NVIDIA RTX 4090) and an edge AI device (NVIDIA Jetson AGX Orin). While GPUs exhibit lower latency, our non-AI-specific accelerator achieves higher energy efficiency, improving the Power-Delay Product (PDP) by up to 44.4× and 13.6× compared with the RTX 4090 and Jetson, respectively. Similarly, it reduces the Energy-Delay Product (EDP) by up to 11.5× compared to the high-performance GPU, demonstrating a favorable performance-energy trade-off. Critically, our system-level analysis identifies host-accelerator data transfer as the primary performance bottleneck, a factor often overlooked in kernel-level studies. These findings provide design guidance for next-generation LLM accelerators. This work validates CGRAs as a suitable platform for LLM inference in power-constrained environments, without being confined to specific algorithms.
@article{ando2025efficient,
author = {Takuto Ando and Yu Eto and Ayumu Takeuchi and Yasuhiko Nakashima},
title = {Efficient Kernel Mapping and Comprehensive System Evaluation of LLM Acceleration on a CGLA},
journal = {IEEE Access},
volume = {13},
pages = {199631--199646},
year = {2025},
doi = {10.1109/ACCESS.2025.3636266}
}
Efficient Kernel Mapping and Comprehensive System Evaluation of LLM Acceleration on a CGLA
04.
"DPU-Based Hardware Implementation for Real-time Facial Expression Recognition System"
Impact Factor: 0.72 (2026)
[en]
In this paper, we implemented a standalone DPU-based facial expression recognition system on SoC FPGA. The system consists of a face detection step and a facial expression recognition step. In conventional FPGA-based facial expression recognition systems, the Haar Cascade detector is run on the CPU due to FPGA (Field Programmable Gate Array) resource limitations in the face detection step. However, the Haar Cascade detector is less accurate than DNN (Deep Neutral Network)-based face detection for images of profile faces and images with changing lighting conditions. On the other hand, face detection using a DNN such as YOLO requires a long latency when executed on a CPU with low computing performance. Therefore, we offload face detection and facial expression recognition by DNN to DPU, a CNN accelerator on FPGA, to speed up the processing. In this work, we combined face detection with DenseBox and CNN-based facial expression recognition on the same DPU. The same DPU was used to implement the facial expression recognition system, which enabled efficient use of FPGA resources while keeping the size of the circuitry.
@article{ando2025dpu,
author = {Takuto Ando and Yusuke Inoue},
title = {DPU-Based Hardware Implementation for Real-time Facial Expression Recognition System},
journal = {ICIC Express Letters},
volume = {19},
number = {4},
pages = {419--426},
year = {2025},
doi = {10.24507/icicel.19.04.419}
}
DPU-Based Hardware Implementation for Real-time Facial Expression Recognition System
2
国内論文誌
応用評価を含む日本語の査読付き論文です。
01.
"エッジデバイス上におけるリアルタイム小ねぎ分岐部位置検出"
[ja]
近年，小ねぎ生産における農業従事者の不足が深刻な課題となっており，人手を減らす小ねぎ調製機の開発が求められている．現行の調製機では一度に不要な葉を全て除去できず，小ねぎを調製機に通した後に，人手による不要な葉を取り除く作業を行う必要がある．二次処理の不要な調製を行うためには，小ねぎの最上部の分岐部位置にノズルを合わせて調製機へ投入することが有効であると分かっている．これを行うには，分岐部の位置は個体によって異なるため分岐部の位置を判別し，位置を揃えて調製機に投入する必要がある．したがって，画像認識により小ねぎ分岐部の位置を検出し，ノズルの位置を自動で合わせることが正確な調製につながると考えた．そこで本稿では，分岐部の検出を目的として，小ねぎ分岐部における特有の斜線を抽出する手法を提案する．本手法は，低消費電力で演算能力の低いエッジデバイスでの実装を目標として，エッジ検出による画像処理をベースとした軽量なアルゴリズムを用いる．本手法を実際の小ねぎ画像に適用して，Raspberry Pi 3で評価した結果，分岐部斜線の検出率は90.6%であり．処理時間は455 msを達成した．この結果より，本手法が分岐部の検出に対して有効であることが明らかとなり，実環境にて応用できる可能性が示された．
@article{ando2024greenonion,
author = {安藤 拓翔 and 井上 優良},
title = {エッジデバイス上におけるリアルタイム小ねぎ分岐部位置検出},
journal = {農業情報研究},
volume = {33},
number = {2},
pages = {73--80},
year = {2024},
doi = {10.3173/air.33.73}
}
エッジデバイス上におけるリアルタイム小ねぎ分岐部位置検出
3
国際会議
CGLA、IMAX、エッジ AI システムに関する国際会議・フォーラム発表です。
01.
"Mamba-Family State-Space Model Kernels on a Programmable CGLA"
[en]
Edge and embedded inference is constrained by power and data movement. Mamba-family state-space models replace attention with sequence-linear recurrence, but their inference path combines dense projections, short-reduction SSD kernels, and recurrent-state updates. This paper maps these kernel groups onto IMAX, a programmable CPU-Grounded Linear Array (CGLA), and measures them from kernel execution to token-level integration. Projection kernels match the long-reduction IMAX pipeline, whereas SSD Step-1 is limited by short reductions and kernel-boundary overheads. Mamba-130M token-level integration identifies projection GEMV as the decode bottleneck. These results show that programmable CGLAs fit long-reduction projection kernels, while SSD and decode-time projection support require boundary reduction and persistent-weight execution.
@inproceedings{ando2026mamba,
author = {Takuto Ando and Yasuhiko Nakashima},
title = {{Mamba-Family State-Space Model Kernels on a Programmable CGLA}},
booktitle = {2026 IEEE 19th International Symposium on Embedded Multicore/Many-core Systems-on-Chip},
year = {2026},
url = {https://arxiv.org/abs/2609.27437}
}
Mamba-Family State-Space Model Kernels on a Programmable CGLA
02.
"Implementation and Evaluation of NTT Arithmetic for ML-KEM on a CGLA"
[en]
FIPS 203 standardizes ML-KEM for post-quantum key establishment. Its polynomial multiplication relies on NTT butterflies with exact modular arithmetic over q = 3329. Dedicated NTT accelerators minimize latency with fixed modular arithmetic and stage schedules. A CPU-Grounded Linear Array (CGLA) reuses one programmable linear datapath across several workloads. Mapping the transform to this datapath requires exact FP32 reconstruction and explicit stage transitions across the ARM-to-CGLA interface. We implement an eight-stage cyclic radix-2 driver over the ML-KEM modulus by splitting each twiddle into 8-bit and 4-bit parts before modular reduction. This driver differs from the standardized seven-layer incomplete negacyclic NTT and does not implement the full ML-KEM polynomial multiplication path. The arithmetic sequence keeps every integer below 2^24. One 41-PE call fuses the first two radix-2 stages, and six 47-PE calls execute the remaining stages while scattering outputs into next-stage records. Across four cohorts, 105 FPGA runs match all 817152 output coefficients. At batch size 64, measured FPGA end-to-end latency is 27.5 us per NTT, and the ASIC projection is 6.74 us. With PE gating, projected ASIC system energy is 10.1 uJ per NTT at batch size 8 and 58.9 uJ at batch size 64.
@inproceedings{ando2026ntt,
author = {Takuto Ando and Yasuhiko Nakashima},
title = {{Implementation and Evaluation of NTT Arithmetic for ML-KEM on a CGLA}},
booktitle = {2026 Fourteenth International Symposium on Computing and Networking Workshops (CANDARW 2026)},
year = {2026},
url = {https://arxiv.org/abs/2609.28904}
}
Implementation and Evaluation of NTT Arithmetic for ML-KEM on a CGLA
03.
"Implementation and Evaluation of BitNet Inference on a CGLA by Signed-Int4 Instructions"
[en]
Large language model (LLM) inference transfers model weights and activations for every generated token, making memory traffic and its energy cost part of the decode path. BitNet b1.58 represents its low-bit weights by ternary values and uses integer activations. However, this arithmetic does not match conventional int8 or floating-point general matrix multiplication, and existing BitNet accelerators implement it in specialized datapaths. We instead map this operation to a CPU-Grounded Linear Array (CGLA), a programmable ASIC with explicit direct memory access, local memories, and reusable compiler-visible integer lanes. The mapping adds OP_SMA4 as a reusable signed-int4 multiply-accumulate instruction rather than a BitNet-only datapath. Each ternary weight occupies one signed 4-bit lane. Each int8 activation is split into two signed-int4 fragments and reconstructed by shift-and-add. Frequency scaling of the 145 MHz FPGA measurement to an 840 MHz 28 nm CGLA achieved 0.390 ns per signed-int4 product. We showed that CGLA-offloaded BitNet C++ execution measures 2.52 tokens/s.
@inproceedings{ando2026bitnet,
author = {Takuto Ando and Yasuhiko Nakashima},
title = {{Implementation and Evaluation of BitNet Inference on a CGLA by Signed-Int4 Instructions}},
booktitle = {2026 Fourteenth International Symposium on Computing and Networking Workshops (CANDARW 2026)},
year = {2026},
url = {https://arxiv.org/abs/2609.27453}
}
Implementation and Evaluation of BitNet Inference on a CGLA by Signed-Int4 Instructions
04.
"Energy-Oriented CGLA Mapping of a Memory-Polynomial Digital Predistortion Kernel"
[en]
Memory-polynomial digital predistortion (DPD) evaluates a small fixed coefficient set over a sliding input history, so its reduction step is a complex-MAC workload with local reuse. We map this DPD reduction kernel onto In-Memory Accelerator eXtension (IMAX), a programmable CPU-Grounded Linear Array (CGLA) composed of a one-dimensional processing-element/local-memory pipeline. For a (P,M)=(5,5) odd-order memory-polynomial instance, the mapping keeps the 120 B coefficient set in local memory, advances the five-tap history over 1024-sample tiles, and realizes the 15 order-delay terms as a 33-stage streaming complex-MAC reduction. The evaluation measures kernel latency and modeled energy. All measured paths use the same single-precision complex workload of 32 sequences, each with 2048 complex samples, across an IMAX FPGA prototype, a CUDA implementation on an RTX 4090 system, and an ARM-NEON implementation on Jetson AGX Orin. With this 1024-sample tile configuration, the IMAX FPGA prototype reports 20.201 ms end-to-end latency and 1.948 ms kernel-only latency. Using the previously reported 28 nm IMAX frequency and power model, the projected IMAX configuration gives 3.14 ms end-to-end latency and 0.34 ms kernel-only latency. The RTX 4090 baseline has the lowest end-to-end latency at 0.484 ms. Under model-based platform power accounting and the stated power assumptions, the projected IMAX configuration gives 169.1 times smaller modeled end-to-end energy per batch than the RTX 4090 baseline. This value uses platform power assumptions rather than workload-dependent runtime power or a direct silicon power measurement. A controlled synthetic PA-model validation checks that the same 15-term form improves test-set NMSE by 26.1 dB and ACLR by 26.0 dB. These results characterize the mapped memory-polynomial DPD reduction on IMAX for the evaluated tile configuration and power model.
@inproceedings{ando2026dpd,
author = {Takuto Ando and Yasuhiko Nakashima},
title = {{Energy-Oriented CGLA Mapping of a Memory-Polynomial Digital Predistortion Kernel}},
booktitle = {2026 IEEE Asia Pacific Conference on Circuits and Systems},
year = {2026},
note = {Poster Paper},
url = {https://arxiv.org/abs/2609.27438}
}
Energy-Oriented CGLA Mapping of a Memory-Polynomial Digital Predistortion Kernel
05.
"Q-snap: Quantization-aware dynamic chunking for LLM execution on a CGLA"
Best Paper Award
Links
PDF
[en]
This paper addresses the critical energy inefficiency of LLM inference on standard GPUs by leveraging a Coarse-Grained Linear Array (CGLA). We identify that static workload chunking in existing frameworks exposes prohibitive data transfer latency overheads on CGLAs. We introduce Q-Snap (Quantization-Aware Dynamic Chunking), a scheduling strategy that maximizes execution burst sizes based on runtime memory constraints and quantization alignment. Using an FPGA prototype and synthesis-based 28 nm ASIC projections, our method achieves a 1.62× speedup over the unoptimized baseline on the same hardware in the prefill phase. Our 28 nm CGLA design demonstrates 27 % better energy efficiency compared to a 4 nm RTX 4090, demonstrating that hardware-aware scheduling enables even mature process nodes to deliver superior sustainability for edge LLM inference.
@inproceedings{ando2026qsnap,
author = {Takuto Ando and Ayumu Takeuchi and Yu Eto and Yoshifumi Munakata and Yasuhiko Nakashima},
title = {{Q-snap: Quantization-aware dynamic chunking for LLM execution on a CGLA}},
booktitle = {Sixth International Conference on Intelligent Systems and Networks},
year = {2026}
}
06.
"Implementation and Evaluation of Stable Diffusion on a General-Purpose CGLA Accelerator"
[en]
This paper presents the first implementation and in-depth evaluation of the primary computational kernels from the stable-diffusion.cpp image generation framework on IMAX3, a general-purpose Coarse-Grained Reconfigurable Array (CGRA) accelerator. We designed IMAX3 as a versatile computational platform, and this work assesses its capabilities by executing a demanding image generation workload. We evaluate its performance on a current Field-Programmable Gate Array (FPGA) prototype to establish a baseline and project its potential for a future Application-Specific Integrated Circuit (ASIC) implementation. Our results demonstrate that, despite its general-purpose architecture, IMAX3 achieves promising performance and power efficiency, particularly in its projected ASIC form. This work provides concrete guidelines for future IMAX architectural designs and establishes a foundation for developing next-generation, AI-specialized CPU-Grounded Linear Array (CGLA) accelerators by refining this versatile platform. Ultimately, this achievement contributes to the realization of energy-efficient, on-device, multi-modal AI platforms.
@inproceedings{ando2025stablediffusion,
author = {Takuto Ando and Yu Eto and Yasuhiko Nakashima},
title = {Implementation and Evaluation of Stable Diffusion on a General-Purpose CGLA Accelerator},
booktitle = {2025 IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)},
year = {2025},
doi = {10.1109/MCSoC67473.2025.00120}
}
Implementation and Evaluation of Stable Diffusion on a General-Purpose CGLA Accelerator
07.
"Energy-Efficient Hardware Acceleration of Whisper ASR on a CGLA"
Best Paper Award
[en]
The rise of generative AI for tasks like Automatic Speech Recognition (ASR) has created a critical energy consumption challenge. While ASICs offer high efficiency, they lack the programmability to adapt to evolving algorithms. To address this trade-off, we implement and evaluate Whisper's core computational kernel on the IMAX, a general-purpose CPU-Grounded Linear Arrays (CGLAs) accelerator. To our knowledge, this is the first work to execute a Whisper kernel on a CGRA and compare its performance against CPUs and GPUs. Using hardware/software co-design, we evaluate our system via an FPGA prototype and project performance for a 28 nm ASIC. Our results demonstrate superior energy efficiency. The projected ASIC is 1.90x more energy-efficient than the NVIDIA Jetson AGX Orin and 9.83x more than an NVIDIA RTX 4090 for the Q8_0 model. This work positions CGLA as a promising platform for sustainable ASR on power-constrained edge devices.
@inproceedings{ando2025whisper,
author = {Takuto Ando and Yu Eto and Ayumu Takeuchi and Yasuhiko Nakashima},
title = {Energy-Efficient Hardware Acceleration of Whisper ASR on a CGLA},
booktitle = {2025 13th International Symposium on Computing and Networking (CANDAR)},
year = {2025},
doi = {10.1109/CANDAR68384.2025.00018}
}
Energy-Efficient Hardware Acceleration of Whisper ASR on a CGLA
08.
"A Detailed Analysis of LLM Execution on IMAX3 and Initial Evaluation of IMAX4 Prototype for Server Environment"
Young Researcher Award
Links
PDF
[en]
In this paper, we present a detailed analysis of the IMAX3 CGRA-based accelerator and the IMAX4 prototype with an upgraded host CPU. To address the host CPU bottlenecks of its predecessor, IMAX3, IMAX4 incorporates a server-oriented Intel Xeon processor and PCIe Gen5 connectivity, realizing IMAX scalability. We implemented and evaluated the IMAX4 prototype using microbenchmarks and the LLaMA3 8B quantized model. The results demonstrate significantly reduced host-side overheads and improved data transfer compared to IMAX3. While performance characteristics vary by quantization, IMAX4 demonstrates significant potential by shifting bottlenecks from the host to data pathways, highlighting the viability of CGRA for server-based LLM acceleration.
@inproceedings{ando2025imaxevaluation,
author = {Takuto Ando and Yu Eto and Yasuhiko Nakashima},
title = {{A Detailed Analysis of LLM Execution on IMAX3 and Initial Evaluation of IMAX4 Prototype for Server Environment}},
booktitle = {The 26th Workshop on Synthesis And System Integration of Mixed Information Technologies},
year = {2025}
}
09.
"Energy-Efficient Llama3 Acceleration on a CGLA by Offloading Computational Kernels"
PDF
[en]
The evolution of Large Language Models (LLMs) has led to a substantial increase in energy consumption, making energy-efficient accelerator technologies essential. We propose a method to maximize the performance of the Llama3 LLM on IMAX3, a CGRA-based accelerator. We conducted a detailed analysis of the Q3_K_S quantization method. Based on this analysis, we implemented a new custom kernel to offload the Q6_K operations to the hardware. In previous work, this operation was processed on the host CPU. This targeted optimization reduced the end-to-end latency by approximately 11%. Furthermore, an evaluation of a projected ASIC implementation showed that the absolute performance does not match that of a GPU. In contrast, our approach achieves superior power efficiency, as measured by the Power-Delay Product (PDP).
@inproceedings{ando2025llama3forum,
author = {Takuto Ando and Yu Eto and Ayumu Takeuchi and Yasuhiko Nakashima},
title = {Energy-Efficient Llama3 Acceleration on a CGLA by Offloading Computational Kernels},
booktitle = {2025 IEEE 38th International System-on-Chip Conference (SOCC) PhD/Master Forum},
year = {2025},
doi = {10.1109/SOCC66126.2025.11235407}
}
Energy-Efficient Llama3 Acceleration on a CGLA by Offloading Computational Kernels
10.
"LLM Performance Bottlenecks on CGLA"
Abstract
PDF
@inproceedings{eto2025bottlenecks,
author = {Yu Eto and Takuto Ando and Yasuhiko Nakashima},
title = {{LLM Performance Bottlenecks on CGLA}},
booktitle = {2025 IEEE 38th International System-on-Chip Conference PhD and Master Forum},
year = {2025}
}
LLM Performance Bottlenecks on CGLA
11.
"Energy-Efficient FlashAttention Acceleration on CGLA"
Abstract
PDF
@inproceedings{takeuchi2025flashattention,
author = {Ayumu Takeuchi and Yu Eto and Takuto Ando and Yasuhiko Nakashima},
title = {{Energy-Efficient FlashAttention Acceleration on CGLA}},
booktitle = {2025 IEEE 38th International System-on-Chip Conference PhD and Master Forum},
year = {2025}
}
Energy-Efficient FlashAttention Acceleration on CGLA
12.
"Performance Evaluation of Flan-T5 in CGLA Based Accelerators"
PDF
[en]
Large Language Models (LLMs) impose significant computational and energy demands, posing challenges for deployment on edge devices. To address this, we explore the feasibility of executing Flan-T5 an instruction tuned encoder decoder LLM on IMAX3, an in memory accelerator based on a Coarse Grained Linear Array (CGLA). By leveraging existing custom instructions and hardware kernels originally developed for LLaMA v2 models, Flan-T5 inference was successfully achieved on IMAX3 without requiring any modification to the hardware instruction set or the high level inference workflow.To the best of our knowledge, this is the first implementation of Flan-T5 on a CGLA based accelerator. Although IMAX3 does not currently outperform CPUs or GPUs in execution speed or power efficiency, our analysis identifies critical system level bottlenecks particularly in host accelerator coordination and memory bandwidth that limit scalability. These findings highlight the architectural generality of quantized kernel designs across structurally distinct LLMs and provide a valuable foundation for future work on energy efficient LLM deployment using reconfigurable accelerators.
@inproceedings{eto2025flant5,
author = {Yu Eto and Takuto Ando and Yasuhiko Nakashima},
title = {{Performance Evaluation of Flan-T5 in CGLA Based Accelerators}},
booktitle = {2025 IEEE 38th International System-on-Chip Conference},
year = {2025}
}
Performance Evaluation of Flan-T5 in CGLA Based Accelerators
13.
"Facial Expression Recognition System Using DNN Accelerator with Multi-threading on FPGA"
[en]
In this paper, we implement a stand-alone facial expression recognition system on an SoC FPGA with multi-threading using a Deep learning Processor Unit (DPU). The system consists of two steps: one for face detection step and one for facial expression recognition. In the previous work, the Haar Cascade detector was run on a CPU in the face detection step due to FPGA resource limitations, but this detector is less accurate for profile and variable illumination condition images. Moreover, the previous work used a dedicated circuit accelerator, so running a second DNN inference for face detection on the FPGA would require the addition of a new accelerator. As an alternative to this approach, we run the two inferences by DNN on a DPU, which is a general-purpose CNN accelerator of the systolic array type. Our method for face detection using DenseBox and facial expression recognition using CNN on the same DPU enables the efficient use of FPGA resources while maintaining a small circuit size. We also developed a multi-threading technique that improves the overall throughput while increasing the DPU utilization efficiency. With this approach, we achieved an overall system throughput of 25 FPS and a throughput per power consumption of 2.4 times.
@inproceedings{ando2024multithreading,
author = {Takuto Ando and Yusuke Inoue},
title = {Facial Expression Recognition System Using DNN Accelerator with Multi-threading on FPGA},
booktitle = {2024 12th International Symposium on Computing and Networking Workshops (CANDARW)},
pages = {103--109},
year = {2024},
doi = {10.1109/CANDARW64572.2024.00025}
}
Facial Expression Recognition System Using DNN Accelerator with Multi-threading on FPGA
14.
"FPGA Implementation of a DPU-Based Facial Expression Recognition System"
Links
PDF
[en]
In this paper, we implemented a standalone DPU-based facial expression recognition system on SoC FPGA. In conventional FPGA-based systems, the Haar Cascade detector is run on the CPU for face detection due to FPGA resource limitations. We offload face detection and facial expression recognition by DNN to DPU, a CNN accelerator on FPGA. The same DPU was used to implement the facial expression recognition system, which enabled efficient use of FPGA resources while minimizing the size of the circuitry.
@inproceedings{ando2024fpgadpu,
author = {Takuto Ando and Yusuke Inoue},
title = {{FPGA Implementation of a DPU-Based Facial Expression Recognition System}},
booktitle = {The 25th Workshop on Synthesis And System Integration of Mixed Information Technologies},
year = {2024}
}
4
国内研究会
実装詳細やシステム評価を整理した国内研究会・大会発表です。
01.
"CGLA上の多様なAIワークロードに向けた統合ソフトウェアスタックの実装と今後の展望"
Links
PDF
[ja]
AI ワークロードの多様化に伴い,推論基盤には電力効率を保ちながら異なるワークロードへ展開できる柔軟性が求められる. GPU は汎用性が高い一方で消費電力が大きく,専用 ASIC は高効率だが対象ワークロードが固定されやすい. FPGA は柔軟だが,動作周波数と実行性能に制約がある. そこで本稿では,これらの中間に位置する CGLA (CPU-Grounded Linear Array) 上で,llama.cpp,whisper.cpp,stable-diffusion.cpp などの ggml 系 OSS を対象に,共通する実装方法と初期評価を整理する. CPU 側の行列積・dot積実装を IMAX へオフロードし,この実装方法を音声認識と画像生成にも適用した. 既存結果より,大規模言語モデルのトークン生成フェーズは LOAD とホスト側処理に支配され,動的チャンク分割によりトークン解析フェーズは 1.62 倍に高速化した. Whisper 音声認識は Jetson AGX Orin 比 1.90 倍,RTX 4090 比 9.83 倍の電力効率を達成した. Stable Diffusion では FP16/FP32/整数型が混在したモデルの実装に成功した. これらを踏まえ,共通のフロントエンド,計測に基づくランタイム,方策に応じて切り替えるバックエンドから成るソフトウェアスタックの論点を示す.
[en]
As AI workloads diversify, inference platforms must provide both power efficiency and the flexibility to support a range of workloads. GPUs are highly programmable but power-hungry, whereas dedicated ASICs are efficient but typically tailored to specific workloads. FPGAs are flexible, but their operating frequency and execution performance are often limited. In this paper, we present a common implementation approach and an initial evaluation for ggml-based OSS workloads on CGLA/IMAX, including llama.cpp, whisper.cpp, and stable-diffusion.cpp. In llama.cpp, we offload CPU-side matrix multiplication and dot-product kernels to IMAX and extend the same implementation boundary to ASR and image generation workloads. Our prior results show that LLM decode is dominated by LOAD and host-side processing, Q-Snap improves prefill performance by 1.62×, Whisper ASR achieves 1.90× and 9.83× higher energy efficiency than Jetson AGX Orin and RTX 4090, respectively, and Stable Diffusion is implemented with mixed FP16/FP32/quantized execution. Based on these observations, we discuss software-stack issues for CGLA, including a common frontend, a measurement-driven runtime, and policy-specialized backends.
@inproceedings{ando2026softwarestack,
author = {安藤 拓翔 and 宗片 吉史 and 中島 康彦},
title = {CGLA上の多様なAIワークロードに向けた統合ソフトウェアスタックの実装と今後の展望},
booktitle = {第257回情報処理学会 システム・アーキテクチャ研究発表会},
year = {2026}
}
02.
"広帯域メモリを用いたCGLAのLLM向けスケーラビリティ評価"
Links
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[ja]
本稿では, CGLAアクセラレータIMAX上でのAIアプリケーション, 特にLLM推論の実行を対象として,3D積層DRAMに代表される広帯域メモリを備えた将来IMAXにおける性能ボトルネックを予測するためのシミュレーションモデルを提示する．評価の結果, 現行IMAXにおいても, メモリ帯域の向上により1.4倍から1.9倍の性能向上が見込まれることを確認した．さらに, 本モデルに基づき, IMAXのスケーラビリティに応じたメモリ構成を検討するための見積り方法を示す．加えて, 将来的に広帯域メモリを導入した際に顕在化すると考えられるホスト側性能のボトルネックへの対応策を検討し,IMAXの並列化およびカスケード接続を組み合わせた二次元的な拡張によるスケーラビリティ向上の方針を提示する．
@inproceedings{munakata2026scalability,
author = {宗片 吉史 and 安藤 拓翔 and 中島 康彦},
title = {広帯域メモリを用いたCGLAのLLM向けスケーラビリティ評価},
booktitle = {第257回情報処理学会 システム・アーキテクチャ研究発表会},
year = {2026}
}
03.
"DNNアクセラレータを用いた表情認識システムにおける電力効率の向上"
学生奨励賞
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[ja]
本研究ではDPUを用いた表情認識システムをSoC FPGA上に実装する．先行研究のFPGAで実装された表情認識システムでは，顔検出の処理をFPGAリソースの制約からCascade検出器を用いてCPU上で実行していた．しかし，この手法ではDNNベースの顔検出よりも精度が劣る．そこで本研究では，DNNによる顔検出と表情認識を同一のDPUで時分割実行することで，リソースを抑えつつFPGAで実行可能なハードウェア構成を提案する．また，全体の消費電力とスループットを向上させるためにマルチスレッドを活用した手法を提案する．本システムは先行研究より消費電力あたりのスループットは約2.4倍の向上を達成した．
@inproceedings{ando2025expressionpower,
author = {安藤 拓翔 and 井上 優良},
title = {DNNアクセラレータを用いた表情認識システムにおける電力効率の向上},
booktitle = {情報処理学会第87回全国大会},
year = {2025}
}
04.
"小ねぎ調製位置検出のためのインスタンスセグメンテーション"
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[ja]
小ねぎの分岐部が葉の重なりによって遮蔽される場合に対応するため、インスタンスセグメンテーションによる調製位置の推定を検討した。Mask R-CNNで芯と葉の領域を推論し、葉の位置と枚数から分岐部位置を推定する。提案手法の有効性を評価する。
発表スライドの目的・提案手法に基づく要約です。原稿に掲載された要旨の転載ではありません。
@inproceedings{ando2024onionsegmentation,
author = {安藤 拓翔 and 井上 優良},
title = {小ねぎ調製位置検出のためのインスタンスセグメンテーション},
booktitle = {電子情報通信学会九州支部学生会講演会},
year = {2024}
}
05.
"FPGAにおけるDPUを用いた表情認識システムの実装"
@inproceedings{ando2024expressionimplementation,
author = {安藤 拓翔 and 井上 優良},
title = {FPGAにおけるDPUを用いた表情認識システムの実装},
booktitle = {情報処理学会第249回 システム・アーキテクチャ研究発表会},
year = {2024}
}
06.
"FPGAによるリアルタイム表情認識システムの実装"
Abstract
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@inproceedings{ando2023expression,
author = {安藤 拓翔 and 井上 優良},
title = {FPGAによるリアルタイム表情認識システムの実装},
booktitle = {電子情報通信学会九州支部学生会講演会},
year = {2023}
}
07.
"エッジ検出を用いたこねぎ分岐部の検出"
Links
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[ja]
近年，こねぎ生産における最低賃金の上昇等雇用環境が変化しており，人件費を抑えるために人手の不要なこねぎ調製機の開発が求められている．現行の調製機では一度に不要な葉を全て除去できず，二次処理のために多くの人手を要する．正確な調製を行うためには，外葉最上部の分岐部位置に調製用ノズル位置を合わせることが有効であることが分かっている．したがって，こねぎ分岐部の位置を検出し，ノズルの位置を自動で合わせることができれば二次処理を必要としない調製機を開発できる．そこで本稿は，分岐部を検出するためにこねぎ分岐部における特有の斜線を抽出する手法を提案する．本手法は，エッジ検出による斜線抽出とラベリング処理を行うことで頑健な検出を行う．本手法を実際のこねぎ画像に適用した結果，分岐部斜線の検出率は 92%であり，分岐部位置を検出できた．
@inproceedings{ando2023onionedges,
author = {安藤 拓翔 and 井上 優良},
title = {エッジ検出を用いたこねぎ分岐部の検出},
booktitle = {情報処理学会第243回 システム・アーキテクチャ研究発表会},
year = {2023}
}
5
学位論文
修士論文、高専本科の卒業論文、専攻科における特別研究論文です。
01.
"AI Application Implementation and Software-Stack Improvements for Energy-Efficient Workloads on a CGLA"
Links
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[en]
Graphics processing units (GPUs) provide high AI inference throughput but consume high power, whereas fixed-function accelerators require redesign for new models and quantization formats. Motivated by this trade-off, this thesis examines the CPU-Grounded Linear Array (CGLA), a programmable accelerator architecture, using its IMAX3 FPGA prototype. We integrated a CGLA backend into llama.cpp, whisper.cpp, and stable-diffusion.cpp. Through their shared GGML matrix-multiplication interface, quantized and FP16 operations are dispatched to format-specific CGLA dot-product kernels. For dispatched quantized operations, the PE pipeline unpacks values, applies scales, and accumulates dot products, while application control and unsupported operations remain on the CPU. Measurements of Qwen3 model inference show that repeated data transfers and host CPU processing constrain decode. Under the 28 nm ASIC projection, CGLA achieves 226× better PDP (Power-Delay Product) and 51.2× better EDP (Energy-Delay Product) than RTX 4090 for Qwen3-0.6B Q3_K_S at 8:1. PDP reductions are also observed in the automatic speech recognition and image generation evaluations, extending the results beyond LLM inference.
@mastersthesis{ando2026master,
author = {Takuto Ando},
title = {AI Application Implementation and Software-Stack Improvements for Energy-Efficient Workloads on a CGLA},
school = {Nara Institute of Science and Technology},
year = {2026},
month = {July}
}
02.
"エッジ検出を用いたこねぎ分岐部の抽出"
Links
PDF
[ja]
近年,こねぎ生産における最低賃金の上昇等雇用環境が変化しており,人件費を抑えるために人 手の不要なこねぎ調製機の開発が求められている.現行の調製機では一度に不要な葉を全て除去でき ず,二次処理のために多くの人手を要する.正確な調製を行うためには,外葉最上部の分岐部位置に調 製用ノズル位置を合わせることが有効であることが分かっている.したがって,こねぎ分岐部の位置を 検出し,ノズルの位置を自動で合わせることができれば二次処理を必要としない調製機を開発できる. そこで本稿は,分岐部を検出するためにこねぎ分岐部における特有の斜線を抽出する手法を提案する. 本手法は,エッジ検出による斜線抽出とラベリング処理を行うことで頑健な検出を行う.本手法を実際 のこねぎ画像に適用した結果,分岐部斜線の検出率は 92%であり,分岐部位置を検出できた.
@misc{andoonionthesis,
author = {安藤 拓翔},
title = {エッジ検出を用いたこねぎ分岐部の抽出},
howpublished = {大分工業高等専門学校 情報工学科},
note = {卒業研究論文 / 指導教員: 井上 優良}
}
03.
"DPUを用いたマルチタスクDNN表情認識システムのFPGA実装"
Links
PDF
[ja]
SoC FPGA上のDPUを用いた表情認識システムを実装した。顔検出と表情分類をそれぞれDNNで実行し、同一のDPUで二つの推論を処理する構成を検討した。
特別研究論文の緒言・システム構成に基づく要約です。この原稿には独立した要旨がないため、原文の要旨とは区別しています。
@misc{andoexpressionthesis,
author = {安藤 拓翔},
title = {DPUを用いたマルチタスクDNN表情認識システムのFPGA実装},
howpublished = {大分工業高等専門学校 専攻科 電気電子情報工学専攻},
note = {特別研究論文 / 指導教員: 井上 優良}
}